Negative pulse edge triggered flip-flop
US6163192A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35606
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.