Protective circuit
US6163446A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
Abstract
A protective circuit is disclosed for protecting an integrated circuit against electrostatic discharge, so-called ESD. The integrated circuit is connected to a supply voltage via a V.sub.cc -pad (2) and an earth pad (3). The protective circuit, which is particularly intended to protect a positively supplied circuit for radio frequency applications against both negative and positive voltage pulses, comprises an input pad (14) and at least one PNP-transistor (20), the input pad being connected to the integrated circuit, and the PNP-transistor being connected with its collector to the input pad, and its emitter to the V.sub.cc -pad or to the earth pad. The base of the PNP-transistor can be connected to its emitter either directly or via a resistor (24), or not be connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.