Firmware controlled transmit datapath for high-speed packet switches
US6163539A · kind A · utility
123Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A datapath packet transmission controller which includes a central processing unit (CPU), a transmit FIFO buffer operative to receive and temporarily store data packets, and a disposition FIFO buffer coupled to said CPU for holding packet disposition commands received from said CPU. The CPU controls reception and storage of data packets in the transmit FIFO buffer, accesses data in data packets in the transmit FIFO buffer, provides disposition commands which control the disposition of packets after storage in the transmit FIFO buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.