System and method for data transfer across multiple clock domains
US6163545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Jan 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/05
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for converting data in one clock domain to a second clock domain comprises a multiplexer which has a select control which is synchronous with a first frequency and is coupled to two bistable registers of which a first is clock controlled in accordance with the first frequency and a second is clock controlled by the second frequency. The data output of the first register is looped back to the second data input of the multiplexer. The select signal operates to couple a data input to the first register whereupon the multiplexer then serves to couple the data output of the first register back to the data input thereof. The arrangement ensures availability of data at the first clock frequency beyond a transition of the second clock frequency. Thus data, preferably multi-bit address data, can be transferred from one clock domain to another with less delay than in customary systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.