DSP interrupt control for handling multiple interrupts
US6163829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20). Once the external interrupt is generated, the CPU will then examine a flag register associated therewith, which flag bits are set only if the interrupt controller (82) has determined that the CPU (20) is to receive the interrupt in accordance with the contents of the gating registers. The CPU (20) will then service the particular interrupts directed thereto by accessing the stored interrupt vectors. Once all C…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.