Two level address translation and memory registration system and method
US6163834A · kind A · utility
50Cited by
5References
4Claims
0Family size
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Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/326
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A two-level memory region registration and address translation method includes a memory handle table and a translation and protection table (TPT). Each memory region registered is associated with a unique memory handle index which accesses one entry of the memory handle table. The accessed entry in the memory handle table stores a memory handle that is combined with virtual addresses in the registered memory region to access TPT entries storing translation data for the virtual addresses in the registered memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.