RAM based error correction code encoder and syndrome generator with programmable interleaving degrees
US6163871A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 1998 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/158
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Encoders, syndrome generators, and methods for generating ECC check bytes and partial syndromes from a user data sector using a single RAM unit. The user data includes a plurality of data bytes. The encoder includes a storage unit and encoder circuitry. The storage unit is configured to receive and store a plurality of interim check bytes. The encoder circuitry is configured to receive the data bytes of the user data sector sequentially and the interim check bytes to generate a plurality of new interim check bytes in accordance with a generator polynomial. The new interim check bytes is generated after each data bytes of the data sector is received. The encoder circuitry is arranged to receive the interim check bytes from the storage unit such that the encoder circuitry generates the new interim check bytes and stores the generated new interim check bytes in the storage unit as the interim check bytes. The interim check bytes stored in the storage unit correspond to the ECC check bytes when the interim check bytes have been generated in response to all the bytes of the user data sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.