SOI device with double gate and method for fabricating the same
US6166412A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.