Semiconductor device with improved noise resistivity
US6166415A · kind A · utility
164Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Nov 2, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Nov 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.