High resolution delay line
US6166573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Jul 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.