FET gate biasing control device for power amplifier
US6166591A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/561
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A novel closed loop FET biasing circuit featuring a standard logic control format for operational mode switching between operating states of an FET power amplifier. In a preferred embodiment, an FET gate bias control device is provided for configuring a gate bias circuit in an FET power amplifier to accommodate a broad range of output power levels, wherein the configuration is responsive to a command which establishes an FET bias condition. The gate bias control device of the present invention comprises a circuit having a controllable switching unit which connects a plurality of resistors in the source-drain voltage circuit portion individually or in parallel to provide a multiple of resistance values each corresponding to one of four amplifier operating modes. The controllable switching unit responds to a set of logic control signals, and therefore greatly simplifies the transition between operating modes, while maintaining FET bias conditions which insure operational stability without problems associated with temperature and loading fluctuations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.