Method and apparatus for providing DC offset correction and hold capability
US6166668A · kind A · utility
26Cited by
2References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Jun 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A direct current (DC) offset correction loop (200) for determining the required amount of DC offset to an analog input signal includes a digital integrator (211) for measuring the amount of DC offset present at the final output of a forward signal path and a hold circuit (213) for controlling the digital integrator (213). The DC offset correction loop (200) provides a constant amount of DC offset correction to the analog input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.