Data acquisition system and method with a selectable sampling rate
US6166673A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved data acquisition system for digitizing and storing analog data at a selectable sample rate. The analog data signal is first digitized at a rate defined by a high-frequency clock signal. A decelerator collects every N digital data samples and outputs the samples to N memory partitions at a reduced rate equal to the original clock frequency divided by N. The N memory partitions are further configured to receive N store-enable signals corresponding to each of the N digital data samples. Each of the N store-enable signals determines whether a memory partition will store the corresponding digital data sample. By choosing an appropriate pattern for the N store-enable signals, only a portion of the generated digital data signals is stored in memory. This results in a selectable effective sampling rate for the analog data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.