Integrated circuit low leakage power circuitry for use with an advanced CMOS process
US6166985A · kind A · utility
26Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention provides a circuit that includes a core circuit and a control circuit coupled to the core circuit. The control circuit reduces a leakage current in the core circuit when the core circuit is in a Sleep mode. The control circuit maintains a logic state of the core circuit when the core circuit is in a Drowsy mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.