Programmable error control circuit
US6167026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | May 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/445
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a loop network system, a method and apparatus for automatic bypass of a node port associated with a hub port when the node port generates a number of errors beyond a threshold level. In one aspect, a programmable error control circuit provides this automatic bypass. The tolerance level is set through programmable parameters including a number of errors as well as a time interval to evaluate the number of errors detected. After a node port has been bypassed by the error control circuit, the error control circuit continues to monitor the error generation of the node port. When that error generation has reached an acceptable tolerance level, the error control circuit automatically reinserts the node port into the loop. The error control circuit provides statistical reporting on the number of errors as well as the number of bypasses generated at a particular hub port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.