Apparatus and method for correcting a phase of a synchronizing signal
US6167101A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Jul 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an apparatus and a method for correcting the phase of a synchronizing signal. A best clock timing on latching the data input can be achieved by the apparatus and the method provided. The apparatus of the present invention includes: a phase adjusting circuit for adjusting the phase; a phase lock loop being responsive to the phase adjusting circuit for generating a clock pulse signal; a latching circuit for generating a latched data pattern of the data input; a comparing circuit for comparing the latched pattern with the data input; and a switching circuit for varying a time delay of the phase adjusting circuit. The method of the present invention includes the following steps. At first, the phase of the synchronizing signal is delayed and a clock pulse signal is generated from a phase delayed synchronizing signal. Next, a test pattern is latched as a latched pattern by referencing the clock pulse signal. The latched pattern is then compared with the test pattern. If the latched pattern is different from the test pattern, a phase delay of the synchronizing signal is adjusted. The above steps of delaying the phase, generating the clock pulse signal, latc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.