External resistor and method to minimize power dissipation in DC holding circuitry for a communication system
US6167134A · kind A · utility
35Cited by
89References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Mar 4, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.