Method and apparatus for leveraging history bits to optimize memory refresh performance

US6167484A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• John Mark Boyer · Austin, US
• William C. Bruce, Jr. · Austin, US
• Grady L. Giles · Austin, US
• Thomas K. Johnston · Austin, US
• Bernard J. Pappert · Austin, US
• John J. Vaglica · Austin, US

Key dates

• Filing date: May 12, 1998
• Grant date: Dec 26, 2000
• Expiry date: May 12, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/24
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.