Parallel access virtual channel memory system with cacheable channels
US6167486A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1996 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Nov 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.