Multi-port RAM having functionally identical ports
US6167487A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Jan 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a SRAM, a DRAM, and two independent and functionally identical IO ports. Each port may be used as a read-only, a write-only, or a read-write port. One port may perform a read access to the SRAM, whereas the other port may carry out a write access to the SRAM in the same clock cycle. Each and every location of the SRAM may be accessed from any of the ports. Each port comprises a two-stage pipelined data path for providing a read or write access to the SRAM. Stage 1 decodes control and write enable signals, latches address signals and performs the output of read data. Stage 2 supports accesses to SRAM cells for writing and reading data. In a unified-port mode of operation, two 16-bit ports may be combined to produce a single port supporting a 32-bit write or read access to the SRAM. In a data burst mode of operation, each port may be programmed to select individual length of data bursts and individual burst type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.