High performance digital electronic system architecture and memory circuit therefor
US6167491A · kind A · utility
Inventor
Key dates
| Filing date | Mar 5, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Mar 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.