Apparatus for convolutional self-doubly orthogonal encoding and decoding
US6167552A · kind A · utility
20Cited by
16References
22Claims
0Family size
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Key dates
| Filing date | Oct 2, 1997 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Oct 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K-bit parallel output to a self-doubly orthogonal code sequence generator. The encoded symbol stream is threshold decoded iteratively using the inversion of the convolutional self-doubly orthogonal parity code generators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.