Method of making a high-voltage transistor with multiple lateral conduction layers
US6168983A · kind A · utility
182Cited by
32References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Feb 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.