Complementary metal-oxide semiconductor buffer
US6169421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.