Method and circuit for regulating the length of an ATD pulse signal
US6169423A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1998 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Nov 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.