CMOS imager column buffer gain compensation circuit
US6169430A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS imager is arranged in a plurality of rows and columns with a gain compensation circuit supplied for each of the column. The gain compensation circuit has a first source follower circuit that employs majority carriers of a first polarity yielding a first voltage gain, and a second source follower circuit employing majority carriers of second polarity opposite the first polarity yielding a voltage gain that is essentially the opposite of the first voltage gain variation as compared to the input voltage. The input to the second source follower circuit that is electrically coupled to the output of the second source follower circuit resulting in a gain compensation between the first and second source follower circuits. A selection circuit is configured to enable the gain compensation circuit upon activation of a column select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.