Semiconductor memory device
US6169684A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.