Self-convergence of post-erase threshold voltages in a flash memory cell using transient response
US6169693A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.