Memory device having a chip select speedup feature and associated methods
US6169702A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of address on-chip receivers (OCRs), an address decoder coupled to the address OCRs, a plurality of first delay circuits coupled between the address OCRs and the address decoder, and a plurality of chip select bypass circuits. Each chip select bypass circuit is respectively coupled to one of the plurality of first delay circuits for initially reducing a delay therein responsive to a control signal. The chip select bypass circuit includes a second delay circuit having a delay less than the first delay circuit, and a disable circuit. The disable circuit disables the first delay circuit and selectively couples the second delay circuit in place of the first delay circuit responsive to the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.