Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy
US6170053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30.sub.r) corresponding to a branch instruction. The information fields include at least a target instruction address (T.sub.n), a prediction field (P.sub.n) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPA.sub.n) indicating accuracy for past prediction fields. In operation, the circuitry for retrieving instructions retrieves (46), as a next instruction to follow the branch instruction, an instruction corresponding to the target instruction address in response to a function (TP.sub.n) responsive to the accuracy measure exceeding a predetermined threshold and the prediction field indicating program fl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.