Planarizing a trench dielectric having an upper surface within a trench spaced below an adjacent polish stop surface
US6171180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention advantageously provides a method for using an abrasive surface and a particle-free liquid to polish a dielectric, wherein the dielectric is deposited within an isolation trench and across a polish stop surface such that a recess region of the dielectric is spaced below the polish stop surface. In an embodiment, the dielectric is an isolation oxide, and the polish stop surface belongs to an upper surface of a nitride layer formed above a silicon-based substrate. The surface of the dielectric is positioned laterally adjacent the abrasive polishing surface such that the particle-free liquid is positioned at the interface between the dielectric and the polishing surface. The particle-free liquid is preferably deionized water, and the abrasive polishing surface is preferably a polymeric matrix entrained with particles composed of, e.g., ceria. A force configured perpendicular to the backside of the substrate is applied to the polishing surface to force the dielectric surface against the polishing surface while the polishing surface is being rotated relative to the dielectric. As a result, elevationally raised regions of the dielectric are polished to the recessed r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.