Integrated circuit varactor having a wide capacitance range

US6172378A · kind A · utility

Assignee

• Silicon Wave, Inc. · US

Inventors

• Christopher Hull · Portland, US
• James D. Seefeldt · Eden Prairie, US
• Kishore Seendripu · Carlsbad, US

Key dates

• Filing date: May 3, 1999
• Grant date: Jan 9, 2001
• Expiry date: May 3, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/66

Abstract

Integrated circuit varactor structures that include either an P-gate/N-well or N-gate/P-well layer configuration formed on an SOI substrate. The varactor structure is completely electrically isolated from the substrate of the IC by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structures. The isolation trenches preferably extend to the oxide layer of the SOI substrate. The P-gate/N-well varactor structure includes N.sup.+ implant regions formed in an N-well implant layer of the varactor. The N.sup.+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the N-well layer where the P-gate is formed over the LOCOS layer. The P-gate may be formed of polysilicon. The N-gate/P-well varactor structure includes P.sup.+ implant regions formed in a P-well implant layer of the varactor. The P.sup.+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the P-well layer where the N-gate is formed over the LOCOS layer. The N-gate may be formed of polysilicon. The P-gate/N-well varactor is ideally suited for use as a binary or digitally-controlled varactor…