Compound domino logic circuit having output noise elimination
US6172529A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.