Semiconductor memory device and regulator
US6172917A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1999 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | May 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.