Semiconductor memory device allowing high-speed operation of internal data buses
US6172918A · kind A · utility
445Cited by
5References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.