Memory array bitline timing circuit
US6172925A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating timing signals for clocking the sensing amplifiers of a SRAM memory array having a plurality of memory cells joined in rows by wordlines and in columns by bitlines including a dummy bitline, a plurality of dummy memory cells joined to the dummy bit column, means for accessing a plurality of the dummy memory cells in parallel to generate a bitline charging current significantly greater than a bitline charging current in a typical operative column of the SRAM memory array, a circuit responsive to current in the dummy bitline for generating a timing signal to sense amplifiers for generating output signals from the operative columns of the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.