Semiconductor memory device with a multi-bank structure
US6172931A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device with multi-bank structure, includes multiple voltage boosting circuits or internal power supply voltage generating circuits, each of which generates a high voltage to be provided to a bank. The respective voltage boosting circuits or internal power supply voltage generating circuits are sequentially selected under the control of a select signal generating circuit which generates select signals corresponding to the voltage boosting circuits by use of a row address strobe signal. According to the above-mentioned configuration, the number of the voltage boosting circuits is less than the number of banks in the memory device. Therefore, the area that the voltage boosting circuits or internal power supply voltage generating circuits occupy on a chip does not increase in proportion to the increase in the number of banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.