Multiple synthesizer based timing signal generation scheme
US6172937A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1999 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | May 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.