Parallel processing of data matrices
US6173372A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Feb 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling first and second processing elements which have associated respective first and second address memories, and associated respective first and second data memories, the method comprising storing first and second pluralities of address entries in the first and second address memories respectively, exchanging a pre-determined number of address entries between the first and second address memories, retrieving data entries from a common data store on the basis of the address entries held in the first address memory, storing the retrieved data entries in the first data memory, and exchanging the pre-determined number of data entries between the first and second data memories, such that the first data memory includes data entries corresponding to the address entries stored in the first address memory, and such that the second data memory includes data entries corresponding to the address entries stored in the second address memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.