Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle
US6173379A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1996 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | May 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including an array of memory cells and a method for copying information within the memory device. Each memory cell includes a first memory sub-cell and a second memory sub-cell. Each memory cell also includes a device that copies information from the first memory sub-cell into the second memory sub-cell. Each memory cell may include a static random access memory (SRAM) cell and may utilize tri-state inverters to make overwriting information easier and reduce power consumption. Each memory cell may also include a second copy device that allows information to be copied from the second memory sub-cell to the first memory sub-cell. The memory device may be provided in a register file of a microprocessor to copy information from an architectural branch register (ABR) file to a speculative branch register (SBR) file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.