Parallel processor with debug capability
US6173386A · kind A · utility
84Cited by
75References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Dec 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.