Circuit configuration with a microprocessor
US6173396A · kind A · utility
1Cited by
12References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement having a microprocessor whose reset terminal is adapted to receive a reset signal from a driving circuit. A simple reset wiring of the microprocessor is implemented in that the reset terminal is additionally connected to a further terminal of the microprocessor which, after the reset terminal has received the reset signal, holds the reset terminal to a defined suppressing level that deviates from the reset level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.