Apparatus for providing error correction data in a digital data transfer system
US6173429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1997 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Mar 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus for providing error correction data in a digital data transfer system. The apparatus receives a clock signal and provides a first signal using the clock signal. Information data is received and a second signal is provided using the information data. The information data is received in groups which each have a first predetermined number of elements. A plurality of .alpha.ROMs provide Galois Field multiples in look-up tables. The .alpha.ROMs are addressed using the first signal to provide a first address component and using the second signal to provide a second address component. Modula mathematics are performed utilizing the values from the .alpha.ROMs to generate error correction data. The error correction data is in groups each having a second predetermined number of elements. A RAM is accessible by a Trellis encoder and has an array for holding the information data elements and error correction data elements. The number of array locations is equal to an integer multiple of the sum of the first and second predetermined numbers. Further, the information and error correction data elements are sent to the RAM in third groups. A first array …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.