Method and apparatus for debugging, verifying and validating computer software
US6173440A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | May 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3672
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new approach for software debugging, verification and validation is disclosed. The present invention utilizes a knowledge-based reasoning approach to build a functional model of the software code for identifying and isolating failures in the software code. The knowledge-based reasoning approach of the present invention uses the software design, which is preferably based upon a flow chart or block diagram representation of the software functionality, to build the functional model. The software block diagram contributes to the functional model by defining the inputs and outputs of the various blocks of code, as well as defining data interconnections between the various blocks of code. In accordance with a method of the present invention, test points are strategically inserted throughout the code, and each test point is associated with a corresponding block of code. Expected values of the test points for an expected proper-operation execution of the computer program are generated. The computer program is then executed on a computer, and the actual values of the test points from the program execution are compared with the expected values of the test points. Failed test points which d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.