Method of manufacturing vertical trench misfet
US6174773A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage. A gate electrode is formed on an exposed surface of the second conductivity type base region, through a gate insulating film. A source electrode is disposed in contact with surfaces of both of the first conductivity type source region and the second conductivity type base region, while a drain …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.