Semiconductor integrated circuit device and method for manufacturing the same
US6175529A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed system LSI, a test data, an address and a memory control signal required for the test of the memory are generated using the divided-frequency output signal of an address generator, i.e., frequency-divider of an external clock, and a mixer circuit for periodically inverting a pass/fail signal as the test result is provided. This enables the test of the memory with a total of 2 pins of input and output in all. Thus, it becomes possible to test the memory and the logic circuit simultaneously at the time of burn-in test thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.