Synchronous semiconductor storage device
US6175534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1999 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Apr 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.