Fast adder/subtractor for signed floating point numbers
US6175851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Feb 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for adding or subtracting numbers in signed floating point notation performs exponent and mantissa handling operations in parallel. The system includes a comparator, for determining a greater-magnitude and a lesser magnitude floating point number, operating in parallel with a selector for performing a one's complement and single-bit shift on a mantissa portion of the lesser-magnitude floating point number. The system further includes a remaining shift circuit, for determining an additional amount by which the lesser-magnitude mantissa portion should be shifted; and a shifter. The system also includes an absolute add circuit, for determining whether an absolute addition or an absolute subtraction is to be performed, and a single-bit shift circuit, for indicating whether a shift of at least one bit is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.