High bandwidth code/data access using slow memory
US6175893A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read-only memory is connectable to a microcontroller data bus and address bus and includes memory circuits for storing a sequential array of code words executable by the microcontroller; memory address decoding circuits for selecting one of the array of code words, and circuits for conveying the selected one to the data bus when a read signal is received from the microcontroller. Circuits are provided for storing an address transmitted by the microcontroller when an address latch signal is received from the microcontroller, the stored address being connected to the memory address decoding circuits. The stored address is incremented each time a read signal is asserted. A microcontroller for executing a program stored sequentially in read-only memory comprises an address bus for providing a next program code word address to the read-only memory; circuits for providing an address latch enable signal to the read-only memory for latching the program code word address, and circuits for providing a read signal to the read-only memory. The address latch enable signal is suppressed when the next program code word address is consecutive with an immediately preceding program code word addre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.