Cache enabling architecture
US6175895A · kind A · utility
0Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Aug 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A cache enabling architecture in which an optical storage reading and/or writing device, a caching processor and a mass writing and reading device are each connected to a data bus. The optical storage reading and/or writing device exchanges information directly with the caching processor over the data bus. The caching uses the mass writing and reading device as cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.